At the 0.18-micron process level, leading-edge device feature sizes become significantly smaller than the wavelength of light used by best-in-class optical-lithography equipment. Design teams usually must scramble for the best solution to address the new subwavelength challenges.
Unfortunately, the two leading techniques-optical proximity correction (OPC) and phase shifting-are usually performed after the design has already been completed.
When OPC and phase shifting are not considered in the design process, problems ensue. Resolving them can require substantial changes to the design, forcing the staff performing OPC and phase shifting to return the design back to the design staff to resolve all the issues.
As the author of our "Implementation" article from Numerical Technologies points out in his NAND-cell example, a phase conflict that occurs within a NAND cell must be resolved in the library cell itself, rather than at every occurrence within the design. That becomes resource-intensive and time-consuming, since most of the design steps have to be repeated. While such an approach may be tolerable for an integrated-device manufacturer, where the fab and design teams belong to the same company and a "throw back" can be accommodated, in the fabless COT market it is not common practice for foundries to send a design back to the fabless design companies for correction. The author points to a number of examples in which many of the requirements of subwavelength technologies must be handled up-front in the IC design stage, while changes can still be made.
The author calls for the entire design methodology to include steps for subwavelength manufacturing. He argues that existing design tools should integrate the following technologies in a transparent manner: silicon simulation, intelligent OPC, phase-smart physical design, and subwavelength-enabled system-on-chip intellectual property and custom blocks.
Specifically, he calls for accommodations to be made in libraries, system-on-chip IP and custom blocks to enable designers to use them transparently. That's because subwavelength processes-including phase shifting, OPC and related silicon effects and modeling-are incorporated in the design process throughout the libraries.
We have to agree that in the new era of subwavelength technology, the design-to-manufacturing flow is affected: The IC design flow is just one part of the entire flow and must be addressed on a system level, along with many other components.
You might want to plan to drop in on an evening panel discussion moderated by Ron Wilson, ISD editorial director, at the ISQED Conference (www.isqed.org) on Tuesday, March 19, at the Double Tree Hotel in San Jose, Calif. Organized by a couple of Intel designers, the panel will discuss the impact of increasing process variation with technology scaling from the aspect of manufacturing, design and design tools. You may just walk away with an understanding of the correlation between what is designed and what gets manufactured.
While you're there, give Ron a nudge and tell him how much you enjoy reading ISD every month, or suggest a way to improve our publication.
http://www.isdmag.com
Copyright © 2002 CMP Media LLC
2/1/02, Issue # 14152, page 2.
